资源列表
uart_ip
- 实现串口通信模块设置，包括频率分频、波特率产生、接口时序要求(Implementation of serial communication module settings, including frequency division, baud rate generation, interface timing requirements)
sdram_ip
- 完成SDRAM的上电配置，状态机编写其读写模块，存储模块，并通过两个异步作为存储和读取的通道(Complete the SDRAM power-on configuration, the state machine to write its read-write module, memory module, and through two asynchronous as a storage and read the channel)
fen
- 分频器,可以实现时钟分频，频率变小则周期变长(Frequency divider, can realize clock frequency division, frequency becomes smaller, then the cycle becomes longer)
AD9832
- AD9832频率计的VHDL驱动，可以调整频率及相位(VHDL driver for AD9832 frequency meter)
IIR滤波器的FPGA设计
- 基于verilog hdl语言对IIR滤波器设计(Design of IIR filter based on Verilog HDL language)
pwm with tb final
- pwm with testbench in verilog ,synthesizable
LMS
- least mean square algo implemented on verilog
sequence detector
- sequence detector in verilog for xilinx
FIR
- FIR filter in verilog for xilinx ise design suit
IIC_Verilog
- I2C接口代码，v e r i l o g(The code of I2C interface, verilog HDL)
djvcb
- Optimization class contains several simple sample programs, On neural network control, Noisy pulse correlation detection signal.
并行滤波器实现
- matlab和FPGA实现并行滤波器，为书籍附源码，禁止用于商业用途哈，交流学习使用()