资源列表
denali_mem_model_example.txt
- Example format of Denali memory models initial memory file content for byte adressable Flash memory
wARM
- 著名的wARM源代码，作者吴瑞祥，Verilog HDL源代码。(Famous wARM source code, author Wu Ruixiang Verilog, HDL source code.)
xapp502配置例程
- FPGA配置例程，VHDL语言，使用CPLD对FPGA进行配置(The FPGA configuration routine, VHDL language, using CPLD on the FPGA configuration)
counter
- Counter example for FPGA with VHDL
ex1_601
- 该程序可产生周期脉冲，脉冲宽度及周期大小可通过改变相关数值调节。(The program can generate periodic pulse, pulse width and cycle size can be adjusted by changing the correlation value.)
Verilog led
- Xilinx ISE开发平台实现4位的led灯循环点亮源代码，测试文件及约束(4 bit LED lamp cycle lighting)
information_box_code1.10
- jibengongnengverilog(jibengongneng verilog)
key_filter
- Verilog实现按键滤波，亲测可用，有需要的可以下载看看(Verilog to achieve key filter)
Sdram
- 在vivado中调用SDRAM的IP核，并通过数据的读入，读出，验证IP核的使用，文件中有仿真结果时序图。(In the vivado call SDRAM IP core, and read through the data, read, verify the use of IP kernel, the file has simulation results sequence diagram.)
adder8
- 基于vhdl的八位加法器，以两个四位加法器为基础(Eight bit adder of VHDL)
B_G
- Binary To Gray Conversion
Xilinx ISE14_7破解文件和步骤已测可用
- 对于xinlinx ise的破解文件和步骤说明，亲测可用(here is a package of xilinx ise which could use to break the boundaries)