资源列表
第2章_Quartus_II_使用方法
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第2章_Quartus_II原理图输入
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第3章__Quartus_II原理图输入法深入
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第5章_QuartusII应用向导(原理图输入方法)1
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full_adder
- 全加器，可以实现数据的加法运算，有来自低位的进位和向高位的进位。(Full adder, data can be added to the operation, there are low from the carry and to the high carry.)
keyboard
- 通过ps2口实现键盘的链接，对FPGA进行输入。(Through the PS2 port to achieve the keyboard link, the FPGA input.)
VGA
- vga code for fpga 3s500e spartan xilinx code verilog tutorial video graphics array in verilog interfacing with fpga xilins spattan 3e very easy to learn
devided
- 一个16位除8位的除法器，能够输出余数和商。(In addition to a 16 bit 8 bit divider, can output the remainder and quotient.by stan)
multiplier_TB
- multiplier testbench
fulladder_TB
- fulladder test bench
adder_sub_TB
- adder/subtractor testbench
m19
- 用VHDL语言实现74LS161的功能，以及用74LS161实现模19计数器的功能(Using VHDL language to achieve the function of 74LS161, as well as using 74LS161 to achieve modulo 19 counter function)