资源列表
Elevador
- Elevator - VHDL Project
sdram_ov7670_rgb_vga_640480
- IIC配置ov7670，图像存储到sdram，并通过vga显示(IIC configuration ov7670, images stored to SDRAM, and displayed through the VGA)
verilog读取bmp图像数据的程序段.txt
- verilog 写的程序段，实现的功能是把bmp图像直接读到数组中。主要是用在仿真过程中，读取图像数据产生video激励用。 代码是个代码片段，只是读取bmp图像部分。 有分的觉得有用的话赏个分，没分的捧个场啦。(read bmp data to array ,used in video stream gen when sim)
có t?ng chi?u dài to?n b? cay v?i
- invalid descr iption, it should be english
2-bit-full-adder-master
- full adder 4 bit one you
lab_3
- full adder 32 bit one you
Ir
- 基于fpga的红外通信，通过红外控制led灯(Infrared communication based on FPGA)
SystemVerilog断言及其应用
- 该书用来阐述如何使用断言，以及断言的语法和示例(The book is devoted to the use of assertions, as well as to the syntax and examples of assertions)
datasheet
- 可测试EMIF接口，包含读写两种时序,1394协议，LM75A(EMIF interface can be tested, including reading and writing two timing)
BreastCancer (1)
- breast Cancer Classification
spartan6_ibis
- Xilinx Spartan-6 FPGA 信号完整性 分析仿真模型(Xilinx, Spartan-6, FPGA signal integrity Analytical simulation model)
spi_MasterSlaver
- 实现3种模式SPI主从模块功能设计，数据位宽8bit，最大SPI时钟频率支持112MHz，采用FSM设计实现。经本人亲测可用，使用于Spartan6——45T系列芯片；(To achieve three modes SPI master and slave module function design, data bit width 8bit, the maximum SPI clock frequency support 112MHz, using FSM design. Prepared b