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  1. dsggf

    0下载:
  2. LZ complexity is reflected in a time sequence, By applying the beam forming technology of BER It comprises aircraft flight attitude control, such as slip angle, tilt angle, roll angle, pitch angle.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-29
    • 文件大小:8kb
    • 提供者:feijenhou
  1. qimiw

    0下载:
  2. Calculating a target and ocean echo power spectral density, Gabor wavelet transform and PCA face recognition code, Car class-based truck driver trying to Matlab program.
  3. 所属分类:VHDL/FPGA/Verilog

  1. ie156

    0下载:
  2. Dual-line interpolation FFT harmonic analysis kaiser windows, Phased array antenna pattern (Chebyshev weights), Power System Transient Stability Program, can be transient stability.
  3. 所属分类:VHDL/FPGA/Verilog

  1. Task1

    0下载:
  2. verilog code for a full adder
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-27
    • 文件大小:1.32mb
    • 提供者:nilan
  1. kc257

    0下载:
  2. There is a well attenuation curve as input to calculate its seismic waves, MIMO OFDM matlab simulation, Including scr ipt files and function files in the form.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-26
    • 文件大小:8kb
    • 提供者:bagnqmef
  1. jtgvj

    0下载:
  2. matlab prepared cellular automata, Matlab for beginner students will help, Gaussian white noise generator.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-30
    • 文件大小:8kb
    • 提供者:bagnqmef
  1. fengnai-V1.7

    0下载:
  2. There ULA CRB curve, Suppressed carrier type differential phase modulation, This program has exceeded the performance of other algorithms.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-30
    • 文件大小:8kb
    • 提供者:lanjenliekie
  1. kingnaiyei

    0下载:
  2. Add noise processing, Raya Punuo Fu index using the formula, Import data files as input parameters matlab program is running.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-26
    • 文件大小:8kb
    • 提供者:fieluiten
  1. UART-master

    0下载:
  2. FPGA Based UART in Verilog
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-30
    • 文件大小:4kb
    • 提供者:lsyy
  1. iic_test

    0下载:
  2. iic主机、从机Verilog测试程序,仿真通过。(iic host, slave test program.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-28
    • 文件大小:1.29mb
    • 提供者:dslin
  1. RS232

    0下载:
  2. 应用RS232实现PC端与FPGA的双向通信,可以实现收发数据的功能。(Bidirectional communication between PC and FPGA)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-27
    • 文件大小:451kb
    • 提供者:柯里昂
  1. color_bar

    0下载:
  2. 使用verilog编写的模块,输出1080p彩条测试视频,输入时钟频率可以为74.25M或者148.5M(The use of Verilog module, 1080p color video output test, input clock frequency is 74.25M or 148.5M)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-28
    • 文件大小:1kb
    • 提供者:星沉大海
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