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  1. xjrsb

    0下载:
  2. Based on matlab GUI interface design, Complete class-based image processing, contains all of the source code, auto image, Related impulse response analysis algorithm and inspection.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-26
    • 文件大小:12kb
    • 提供者:jienenfui
  1. ndbwu

    0下载:
  2. Including scr ipt files and function files in the form, Clustering analysis based on Euclidean distance, Waveform data analysis.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:
    • 文件大小:12kb
    • 提供者:jienenfui
  1. I2C

    0下载:
  2. i2c master,支持多种波特率,支持arbitration。(I2C master, support a variety of baud rates, support arbitration.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-20
    • 文件大小:7kb
    • 提供者:shuli198349
  1. lcd

    0下载:
  2. lcd控制器,包含initial和control模块,上电后自动画出initial ram里面的图像。(LCD controller, including the initial and control modules, power automatically painted initial ram inside the image.)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-23
    • 文件大小:8kb
    • 提供者:shuli198349
  1. jeday

    0下载:
  2. This is the second energy entropy matlab code, Signal Processing ESPRIT method, GSM is GMSK modulation signal generation.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-18
    • 文件大小:11kb
    • 提供者:tougaofao
  1. yui_dy42

    0下载:
  2. Linear array using cut than learning laid upon the right control of the main sidelobe ratio, Analysis of the signal time domain, frequency domain, cepstrum, cyclic spectrum, etc. Using high-order cumulants of MPSK signal modulation recognition.
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-12
    • 文件大小:11.21kb
    • 提供者:taomunlennen
  1. I2Csalve.v

    0下载:
  2. Modified I2C salve design 1. Asynchronous design: ASIC or FPGA design option 2. 8 bits CSR RW interface: 0~15, address and control 3. PAD not included 4. Altera CPLD verified
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-28
    • 文件大小:2kb
    • 提供者:ph5077
  1. 超声波电源程序基础

    0下载:
  2. msp430单片机计算频率控制字 然后将控制字传递给dds芯片合成高频电信号(The MSP430 microcontroller calculates the frequency control word, and then passes the control word to the DDS chip to synthesize the high frequency electrical signal)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-27
    • 文件大小:2kb
    • 提供者:黄正辉
  1. 标准SDR SDRAM控制器参考设计,Lattice提供

    0下载:
  2. 说明: SDR SDRAM 控制器 来自lattice 已经分析代码可用!大家可以参考修改,形成自己的实例(Descr iption: SDR SDRAM controller from lattice has been analyzed code available, we can refer to modify, to form their own examples)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-24
    • 文件大小:17kb
    • 提供者:modelsim
  1. idkdt

    0下载:
  2. SNR largest independent component analysis algorithm, Calculated transmission characteristics and reflection characteristics of the one-dimensional photonic crystals, Including quaternion various calculations.
  3. 所属分类:VHDL/FPGA/Verilog

  1. rgb_to_ycbcr

    0下载:
  2. RGB转Ycbcr实验,基于av6045开发板例程。(RGB to ycbcr base av6045)
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-19
    • 文件大小:4.65mb
    • 提供者:tonykingzhao
  1. variable_duty_cycle_pwm

    0下载:
  2. VHDL project in ISE Xilinx for PWM generation
  3. 所属分类:VHDL/FPGA/Verilog

    • 发布日期:2017-12-25
    • 文件大小:506kb
    • 提供者:sameer
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