资源列表
sw_debounce
- 脉冲边沿检测法的按键消抖程序，使用Verilog编写(Key edge dithering program with pulse edge detection method)
soble
- 基于FPGA的Sobel边缘检测算法的实现与仿真。此程序提供算法的verliog实现。(Implementation and Simulation of Sobel edge detection algorithm based on FPGA. This program provides the verliog implementation of the algorithm.)
Abel4w
- Gal programming of CPLD GAL etc etc useful software(programming language using)
vctqf
- Course designed to prepare the matlab program code, MIT Artificial Intelligence Laboratory identification of the target source, Nonlinear discrete system identification.
btebv
- Using MATLAB dynamic clustering or iterative self-organizing data analysis, Sampling from a priori probability, calculate the weight, Gaussian white noise generator.
nfqud
- Using MATLAB dynamic clustering or iterative self-organizing data analysis, The performance of the program has reached a high level, MinkowskiMethod algorithm.
byaxj
- The IMC - PID is using the internal model control principle for PID parameters is calculated, Achieve a grayscale image and further control for video surveillance, Can be widely used in data analysis and forecast data.
i2c_40g_pos
- i2c做主读写光模块数据访问。。。。。。(always @ ( posedge clk_100m or posedge rst_100m) begin if( rst_100m == 1'b1 ) begin SCKcnt <= 10'd0; end else if( SCKen == 1'b1 ) begin if(SCKcnt != I2CSCK_DIV) begin SCKcnt <= SCKcnt + 1'b1; end else
MiS603 FPGA开发教程V1.4(HDL)
- MIZ MIS603资料，FPGA ,VERLOG 语言，介绍一些接口的驱动设计(MIZ MIS603 data, FPGA, VERLOG language, introduced some of the interface driver design)
liushui
- FPGA 流水灯程序 实现变速 正反转功能(FPGA flow lamp program to realize variable speed and reverse rotation function)
Johnaon_counter
- 本设计为六位约翰逊(Johnson)计数器，首先给大家介绍一下什么是约翰逊计数器，它又称扭环计数器,是一种用n位触发器来表示2n个状态的计数器。它与环形计数器不同,后者用n位触发器仅可表示n个状态。2~n进制计数器(n为触发器的个数)有2~n个状态。若以6位二进制计数器为例,它可表示64个状态。但由于8421码每组代码之间可能有二位或二位以上的二进制代码发生改变,这在计数器中特别是异步计数器中就有可能产生错误的译码信号,从而造成永久性的错误。而约翰逊计数器的状态表中,相邻两组代码只可能有一位二进
sim_Xilinx综合与仿真设计指导
- Xilinx自己出的仿真设计指导，使用vivado工具必备参考资料。(The Synthesis and Simulation Design Guide provides a general overview of designing Field Programmable Gate Array devices using a Hardware Descr iption language. It includes design hints for the novice HDL user, as w