资源列表
KEBIANCHENGLUOJIQIJIANPEIXUN
- 参加电子设计大赛不可或缺的可编程逻辑器件的系统培训资料-System training materials to participate in Electronic Design Contest integral programmable logic devices
StateMachine
- VERILOG语言，ISE13.4实现的步进电梯的状态机，可以仿真。-VERILOG language, ISE13.4 achieve step elevator state machine can be simulated.
AS-SSD-Benchmark
- this APP likes shit do you like you can eatand happy go fucking it -this APP likes shit do you like you can eatand happy go fucking it
Camera_Logic
- 双目视觉成像，双目视觉摄像头，3D摄像头对应的FPGA图像采集逻辑程序。1> 适用于：单目和多目视觉系统。2> 附图为双摄像头系统，应用了两条图像控制流水，源码对应图中红色的逻辑块，本人已实测代码为OK。-Imaging binocular vision, binocular vision camera, 3D camera image acquisition corresponding FPGA logic program. Applies to: monocular vision
apb
- These are the files of apb verification environment. Some of them are useful as a reference for creating the other verification environment.
nco_sin
- 正弦波发生器，利用quarter ii编译仿真可以产生正弦波图像-Sine wave generator, using quarter ii compile simulation can generate sine wave images
nco-cos
- 余弦波发生器，利用vhdl仿真软件可以产生余弦波图像-Cosine wave generator, the use of VHDL simulation software can generate cosine wave images
dds
- 数字频率合成器设计，可实现各种频率正弦波的生成，亲测可用-Digital frequency synthesizer designed to achieve a variety of frequency sine wave generator, pro-test available
LED
- 基于VHDL语言，利用Vivado开发的16位跑马灯-A 16-running-lights program based VHDL which is developed by vivado
FFT
- 使用Verilog硬件描述语言实现信号处理中的FFT信号的变换-Using Verilog hardware descr iption language conversion signal processing FFT signal
srl2pal
- 数据流串并转换的实现方法多种多样，根据数据的排序和数量的要求，可以选用移位寄存器、RAM等来实现。对于数据量比较小的设计来说，可以使用移位寄存器完成串并转换；对于排列顺序有规定的串并转换，可以用case语句判断实现；对于复杂的串并转换，还可以用状态机实现-Serial data stream and converts a variety of implementations, according to the sort and quantity of data requirements, you
syn_rst
- 指定同步复位时， always的敏感表中仅有时钟沿信号，仅仅当时钟沿采到同步复位的有效电平时，才会在时钟沿到达时刻进行复位操作-Specifies synchronous reset, always sensitive to the table is just a clock edge signal only when the clock along to pick active level synchronous reset, the clock edge arrival time will