资源列表
Black-gold-Sparten6_VerilogV1.6
- 黑金Sparten6开发板Verilog教程V1.6，黑金FPGA教程，多种实例讲解，非常经典实用。-Black Gold Spartan6 board Verilog tutorials V1.6, black gold FPGA course, a variety of examples to explain, very classic and practical.
ax516_20150304A
- 黑金ax516开发板原理图20150304A，需要的同学赶快来下吧。-Black Gold ax516 development board schematics 20150304A, students need to hurry to the next bar.
Quartus_II_12.0PQsys_Nios_II
- 特权同学经典教程，《Quartus_II_12.0+Qsys及Nios_II教程》,需要的同学赶快来下载吧。-Privileged students Tutorial classic, Quartus II 12.0+ Qsys and Nios II Course , students need to hurry to download it.
ddr2
- ddr2 仿真模型，适应于modelsim 仿真，内涵仿真核源码-ddr2 simulation model adapted to the modelsim simulation, simulation connotation nuclear source
timing_constraint
- 三速以太网时序约束参考设计，内涵quartus ii 工程，sdc文件-Triple-Speed Ethernet reference design timing constraints, content quartus ii project, sdc file
ASI
- 异步串行接口ASI,QUARTUS cv demo参考设计，实现ASI传输，完成8b/10b转换，串并转换-Asynchronous Serial Interface ASI, QUARTUS cv demo reference design, implementation ASI transmission, complete 8b/10b conversion, serial-parallel conversion
ASI_simulation
- 异步串行接口ASI仿真设计,quartus modelsim 仿真参考设计，实现ASI传输，完成8b/10b转换，串并转换-Asynchronous Serial Interface ASI simulation design, quartus modelsim simulation reference design, implementation ASI transmission, complete 8b/10b conversion, serial-parallel conversion
ahb_bus
- ahb总线代码,现支持4个master，可扩展-ahb bus verilog module
filtra-lowpass
- this a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR-this is a lowpass filtre in VHDL code with a test_bench you will find some specifications of the FIR
CrossClockDomain
- 跨时钟域设计不错的设计，进过modelsim仿真通过。-Cross-clock domain design is good design been to modelsim simulation through.
sdr_ctrl_latest.tar
- SDRAM控制器设计源码，内含仿真代码，测试通过-SDRAM controller design source code, include simulation code, test by
1
- 基于FPGA的花样流水灯，实现多种8个LED多种方式流动的 verilog程序。-FPGA-based pattern water lights, LED achieve a variety of eight various ways flow verilog program.