资源列表
slavefifo
- FPGA 3D camera experiment
mt46v16m16p_ddr
- 官网下载的，经过板级验证的ddr control mt45v16m16p源代码，verilog语言设计，希望可以用到系统化设计。-Official website to download, through board-level verification ddr control mt45v16m16p source code, verilog language design, hoping to use systematic design.
vhdl_CRC_generatir
- CRC 產生器，VHDL 語言， 適合 FPGA 練習使用-CRC generator , VHDL language, Good for FPGA learnning
reg
- 8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Serial In, and Serial Out- 8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Serial In, and Serial Out
DE2_115_TV
- DE2_115_TV用于de2-115开发板-DE2_115_TV for de2-115 development board
MUSIC1--finish
- 音乐计算器，当输出分别为正负数时，用蜂鸣器响起两段不同的音乐。计算器可实现0~999范围内的加减与或比较功能，并支持连续运算。-Music calculator
xapp859
- V5 DMA例程 Verilog及上位机软件-V5 DMA！！！！！！！！！！！！！！！！！！！！！！！！！！
hdmi_test
- HDMI时序及其仿真文件，可在显示器上显示色彩图形，时序标准为CEA861-D。-HDMI timing and simulation files, can be displayed on the monitor color graphics, timing standards for CEA861-D.
dac8552
- FPGA中利用状态机实现串并转换，读取dac8552数据-FPGA utilizing state machine string and conversion, data read dac8552
clock--jiaoshi
- 基于verilog简单数字时钟程序，可实现校时，校分功能-Based verilog simple digital clock procedures, can be achieved when the school, school division function
lab1
- 这是一些system generator 入门实例，主要给初学者一些参考-Here are some examples of entry-system generator, mainly for beginners some reference
lab2
- 上传的文档以及代码是利用system generator来实现一些简单功能的实例，主要给system generator初学者一些参考-Here are some examples of entry-system generator, mainly for beginners some reference