资源列表
digital-clock
- Digital clock vhdl code
traffic
- traffic vhdl code -traffic vhdl code ......
kb
- 基于niosII系统的PS2键盘测试程序，测试PS2键盘与niosII内核的通信是否成功。该程序在Quartus自带的eclipes下编译运行。-Based nios II system PS2 keyboard test procedures, test PS2 keyboard and niosII kernel communication is successful. Compile and run under Quartus comes eclipes.
12_24clock
- 基于FPGA的数字万年历设计。可显示年月日时分秒星期，可校时，可整点报时。-FPGA-based design of digital calendar. Displays the date when the minutes and seconds the week, when the school can be the whole point timekeeping.
wenduji
- 基于FPGA的温度计设计。感温原件测量环境温度并显示在七段数码管上，可选择华氏温度或摄氏温度显示，超过预设温度有提示音，超过温度上限后会发出警报。- FPGA-based design of the thermometer. Original ambient temperature measured and displayed on the seven-segment LED, selectable Fahrenheit or Celsius temperature display, tem
fft_core_test
- 基于FPGA的FFT的IP核实现，有其详细源码，采用verilog语言编写，内容详细-The FFT based on FPGA IP core implementation, has its source in detail, using verilog language writing, detailed content
24T
- 24小时周期时钟设计，通过quartus模块实现24小时周期时钟，包含模拟的时钟脉冲。-24 hour cycle clock design, through the quartus module to achieve a 24 hour cycle of the clock, including analog clock pulse.
Ripple-carry-adder
- Ripple carry adder using system verilog
Sequential-Multiplier
- sequential multiplier using system verilog
state_led_one
- 基于verilog HDL的状态机8位流水灯（一个按键控制左转和右转），开发环境Diamond 3.7(64-bit)；FPGA采用LCMXO2-1200HC-4MG132C；时钟25M；开发板：与非网小脚丫-Based verilog HDL state machine eight light water (a key control buttons turn left and turn right), the development environment Diamond 3.7 (64-b
write
- 使用golang生成一个coe文件，初始化rom。其中随机产生10000个数值作为初始化值-Use golang generate a coe file to initialize rom. Wherein the randomly generated value as the initial value 10000
source
- FPGA串口，verilog HDL串口收发程序-FPGA serial, verilog HDL serial transceiver procedures