资源列表
vga显示实验及代码
- 里面有具体的关于VGA显示的实验说明及代码，基于verilog HDL语言，里面有三个实验及代码
ad_spi
- AD2548 SPI读写时序 VHDL-AD2548 SPI
fir_filter
- 基于d builder的fir滤波器的设计；fpga高级编程-Based dspbuilder of fir filter design fpga Advanced Programming
music_player
- 基于d builder的音乐播放器的设计；FPGA与matlab联合编程；-Dsp builder based music player design FPGA and matlab joint programming
clock_gyc_system
- 基于用户自定义模块的实时时钟的设计；Qsys硬件设计；-Custom real-time clock module-based design Qsys hardware design
display
- vivado 7-BCD 数字显示代码。可显示4位十进制数字。输入二进制位数可自行修改。-vivado 7-BCD Digital display code。It can display four decimal digits. Enter the number of bits to modify.
DDS
- DDS信号源实例，采用Quartus II开发环境-DDS signal source instance using Quartus II development environment
SensorTemperatura
- Temperature sensor of a FPGA nexys 4 on verilog languaje
src
- 基于VHDL的4*4矩阵按键识别，按键与LED相对应，每按一个按键，对应LED亮一次。-Corresponding VHDL-based 4* 4 matrix identification keys, buttons and LED, each press of a button, the corresponding LED lights up again.
dds_generater
- 波形发生器，可以生成正弦波、三角波、方波、锯齿波；可以选择输出频率和幅度，基于DDS设计，verilog和QuartusII开发-Waveform generator can generate sine, triangle, square wave, sawtooth wave you can the output frequency and amplitude, DDS-based design, verilog and development QuartusII
project-main-doc
- The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is
Runlength-Data-Compression
- The name of the project is “RUN LENGTH ENCOADING”. In this project transmit the data use different compression Techniques. In these Techniques input date is to be encoded. By use the techniques the input data is to be compress .In this project it is