资源列表
weimafashengqi-achieved-by-verilog
- 该代码用Verilog语言实现了M序列的伪码产生，伪码特征方程为X13 +X7+X5+1，已通过仿真验证。-The code in Verilog realize the M-sequence pseudo-code generation, pseudo-code characteristic equation for the X13+ X7+ X5+ 1, it has been verified by simulation.
UART_send
- 串口单字节发送数据。已测试通过。编程预言是Ｖｅｒｉｌｏｇ。-Single-byte serial transmit data. It has been tested. Programming language is Verilog.
UART_rec
- 用Verilog语言写的串口接收程序。通过串口助手发送数据，在数据输出端可以看到发送的数据。（需要自己分配FPGA引脚)-Verilog language used to write the serial receiver. Send data through the serial port assistant. It can be seen at the data output terminal of the data transmission. (Need to assign your ow
AlertLogPkg
- osvvm alert packages that is helpful for vhdl verification
CoveragePkg
- osvvm coverage packages that is helpful for vhdl verification
frequency-generation
- 基于VHDL语言的分频器，输入四位比特控制产生相应的输出频率。-Frequency divider based on VHDL language, input control four bits to produce the corresponding output frequency.
traffic
- 用quartusII编写，实现双向交通灯运行，仿真ok，可以直接下板子-Quartus II with a written two-way traffic lights running simulation ok, directly under the board
CRC
- crc冗余检验，可以进行15,16位的检错，仿真ok-crc redundancy check can be 15, 16-bit error detection, simulation ok
example19-LCD1602
- 基于verilog HDL的LCD1602显示程序，调试通过，可直接调用。-Based verilog HDL of LCD1602 display program, debugging through, can be called directly.
example17-DS1302_ok
- FPGA verilog HDL开发的时钟芯片DS1302程序，调试可用。-FPGA verilog HDL developed clock chip DS1302, debuggers are available.
example20-LCD12864
- FPGA 12864lcd驱动程序，verilogHDL语言开发，可直接使用。-FPGA 12864 lcd driver, verilog HDL language development, it can be used directly.
example14-ADC-ok
- 基于verilog HDL开发的ADC tlc549程序控制，已经调试通过。-Based verilog HDL developed ADC tlc549 control program has been adopted debugging.