资源列表
Simple-design-of-traffic-lights
- 交通灯的显示有很多方式，如十字路口、丁字路口等，而对于同一个路口又有很多不同的显示要求，比如十字路口，车子如果只要东西和南北方向通行就很简单，而如果车子可以左右转弯的通行就比较复杂，本实验仅针对最简单的南北和东西直行的情况。-Traffic lights show there are many ways, such as intersections, T-junction, etc., and for the same intersection there are a lot of differ
Multiplier
- 设计一个能进行两个十进制数相乘的乘法器，乘数和被乘数均小于100。-Can design a multiplier multiplying two decimal numbers, the multiplier and multiplicand are less than 100.
DEMUX1_4
- this project about demultiplexer one to four compiled and implanted in cart fpga xilinx 3E, with file .bit
MUX4_1_2bits_fonction
- this project about multiplexer four to one compiled and implanted in cart fpga xilinx 3E, with file .bit
m_counter
- this project about compteur m bit compiled and implanted in cart fpga xilinx 3E, with file .HDL and .bit
diviseurFrquence50MhzTo1hz
- this file about frequency divider 50 MHz to 1 Hz used in 7-segment display
jiecheng
- 利用Verilog语言中的函数调用实现阶乘运算的功能-Function calls use Verilog language implementation of the factorial function computing
niosLED
- FPGA 实现LED，好用的东西 ，好用的东西 -FPGA LED
cic_40Mhz
- 40MHz的CIC滤波器的FPGA设计，内容很完备-CIC filter of FPGA design in 40MHz，content is complete
fir
- FIR滤波器的fpga设计，内容和代码十分完备-fpga design FIR filters, the content is complete
keshengsheji
- 基于altera公司的cycloneIII的课程设计，主要功能是选手抢答，有倒计时功能，一名选手抢答后其他人无法抢答，倒计时同时停止，若没人抢答，则倒计时归位。-altera company cycloneIII curriculum design based on main function is to answer the players, there is a countdown, after a player who was unable to answer other answer,
mux4_to_1
- this files in quartus2 are 4 to 1 mux