资源列表
audio_test
- FPGA WM8731 CODEC 录音放音demo-FPGA WM8731 CODEC record & play demo
DDS
- DDS,一项关键的数字化技术，全数字化实现、便于集成、体积小、重量轻。-DDS，A key digital technology, all-digital implementation, ease of integration, small size and light weight.
rx_uart
- rx_uart。uart是通用异步收发传输器，是电脑硬件的一部分。-rx_uart.uart is a universal asynchronous receiver transmitter, is part of the computer hardware.
fulladd
- this files in Quartus2 are fulladder
decoder_7_SEG_1
- this files in Quartus 2 are decoder
keypad_7segdis
- this files in Quartus 2 are KEYPAD
ALU_2016
- this files in Quartus 2 are ALU
I2C-Master
- I2C Master for Metis to setup MCP4661
MUX_ise12migration
- mux for fpga vhdl code-mux for fpga vhdl code
counter-achieved-by-verilog
- 该代码用Verilog语言实现了计数功能，主要实现29为计数，已通过仿真验证。-The code in Verilog realize the counting function, the main achievement of 29 counts, has been verified by simulation.
divider-achieved-by-verilog
- 该代码用Verilog语言实现了分频功能，主要实现对输入时钟的54分频，已通过仿真验证。-The code in Verilog realize the crossover functions, the main achievement of the input clock frequency of 54 minutes, has been verified by simulation.
shfiting-output-achieved-by-verilog
- 该代码用Verilog语言实现了移位输出功能，主要实现对输入信号进行移位输出，已通过仿真验证。-The code in Verilog realize the shift output function, the main achievement of the input signal shift output has been verified by simulation.