资源列表
FPGA_JOW74160
- 本设计使用了74160期间设计数字钟，并对该设计进行波形仿真，使用QUARTUS ii 设计软件，对于用单元逻辑器件设计数字钟有帮助-This design uses 74160 period design digital clock, and the design of waveform simulation, the use of II QUARTUS design software, the design of the digital clock with the unit logic d
key_board
- 本设计是实现一个4*4矩阵按键键盘设计，将矩阵按键的按键值通过串口发送到上位机-The design is to achieve a 4*4 matrix keyboard design, the matrix keys to the value of the button to send to the host computer through the serial port
20150608
- 使用VHDL设计双通道高速ADC采集电路，将模拟数据采集，USB发送到计算机- Using VHDL to design a dual channel high-speed ADC acquisition circuit, the analog data acquisition, USB sent to the computer
EDA
- 用VHDL语言编写的各种小模块，有走马灯，计数器，循环寄存器等-VHDL language with a variety of small modules, there is a revolving door, counters, registers, and so the cycle
Zynq-7000-for-Hardware-Engineers
- Zynq-7000硬件工程师step by step教程-Zynq-7000 Extensible Processing Platform Design Workshop for Hardware Engineers
Zynq-7000-for-Software-Engineers
- Zynq-7000软件工程师step by step教程-Zynq-7000 Extensible Processing Platform Design Workshop for Software Engineers
SPI_ROM
- FPGA实现非标准SPI总线数据的接收和解码，并实现ROM数据的读取和执行-FPGA implementation of non-standard SPI bus to receive and decode the data, and to achieve ROM data read and
rec
- 8点8位的FFT，verilog语言，经过Quartus仿真验证-8 piont 8 bits of FFT, verilog language, through the Quartus simulation
shuzizhong
- 基于basys2的简易数字钟，包含校时功能-A simple digital clock base on basys2 board, including timing function.
Additionneur_ise12migration
- additionneur code vhdl for fpga-additionneur code vhdl for fpga
multiplexuer_ise12migration
- multiplixeur vhdl code for fpga-multiplixeur vhdl code for fpga
Clock
- 该程序主要是用Verilog HDL语言编写的多功能数字钟，包括校时，调试，整点报时和万年历模块。-The program is mainly used Verilog HDL language multifunction digital clock, including at school, debugging, the whole point timekeeping and calendar modules.