资源列表
ISE_lab6
- 加法器的VHDL源代码 适合本科生学习使用-Adder VHDL source code for undergraduate learning to use
conv313
- 卷积码编译码（3，1，3）的编码verilogHDL程序-Convolution code codec (3,1,3) coding verilog HDL program
lcd1602_testshiyan4
- 液晶lcd1602的verilogHDL显示程序-verilog HDL lcd1602 liquid crystal display program
dianzhenshiyan5
- FPGA实验的点阵实验verilog程序-FPGA experimental microarray experiments verilog program
DA_TLC5620shiyan3
- FPGA实验DA tlv5620的实验程序-The experimental procedure DA tlv5620
_Modelsim
- modelsim仿真软件使用的参考基本例程-modelsim reference software routines
estruct
- Ejemplo sencillo de encender un led en VHDL
f1
- 简单的宽脉冲状态同步机，输入信号通过两个D触发器到输出。附仿真结果图。-Synchronizer to deal with wide pulse signal.
fh2
- 窄脉冲状态同步机，输入信号通过三个D触发器到达输出端口。-Syhchronizer to deal with narrow pulse signal.
tcd1206
- tcd1206的verilog 驱动，已测试通过，需要的可以相互学习借鉴一下-the driver of tcd1206d(verilog),which had been tested
ethernet
- opencore上实现以太网mac层的开发版Verilog代码，含英文设计文档与datasheet。可在Modelsim中编译与仿真。-Achieve opencore Ethernet mac layer development version of Verilog code, design documents containing English and datasheet. Can be compiled with the simulation in Modelsim.
stopwatch
- 在FPGA上实现秒表，有分秒毫秒三中不同显示。仅供参考，不算优质的代码-Realize stopwatch on FPGA, minutes and seconds there are three different display milliseconds. For reference only, not the quality of the code