资源列表
rom_255
- 入通过键盘控制或者通过50MHz晶振分频后以每1秒步长发生变化，通过8位并口输出数字信号，并将该数字信号经过译码电路后用七段数码管提示输出信息。-By controlling the keyboard or by 50MHz crystal occur long after the division to change every second step, through the 8-bit parallel digital output signal, and the digital sign
mux_2to1
- 2选1的数据选择器 即当s＝1时，输出m＝y；当s＝0时，输出m＝x。 -Data selector 2-to-1 that is, when x = 1, the output m = y when s = 0, the output m = x.
char_7seg
- 七段数码管显示 显示简单字符 显示0～9数字 循环显示4个字符 -Seven-segment LED display simple characters, 0-9 digital loop display four characters
bcd_add_1bit
- 二进制码到BCD码的转换 1位BCD加法器 2位BCD加法器-BCD code to binary code conversion of a BCD adder two BCD adder
Altera DE2 TV BOX with Effects Project
- Altera DE2 TV BOX with Effects Project maintaied for Cyclone 2
ADP5052.PDF
- 多路稳压输出，可配置个电压，非常适合用于fpga电源-Multiple regulated output voltage can be configured very suitable for fpga power
project_wave
- 波形发生器，生成三角波和正弦波,功能较为简单，可以通过改变频率控制字来改变输出波形状态-Waveform generator to generate triangular wave and sine wave
2016sell
- 此售货机模块包括：投币处理模块，商品选择模块，投币模块，分频模块，控制器模块，计时模块，LED灯显示模块，找零模块，出货模块，-The vending desktop module includes: coin processing module, product selection module, coin module, frequency division module, controller module, timing module, the LED display module, t
CRC
- 在数据通信过程中，数据校验是必不可少的部分，CRC校验是一种高效的检验方式。-In the process of data communication,data verification is an indispensable part, CRC verification is an efficient way to test.
LBG64_double_CLK
- 数据压缩算法的硬件实现ASIC&FPGA（矢量量化算法）-Data compression algorithm implemented in hardware ASIC & FPGA (vector quantization algorithm)
wireless_FPGAcode
- 无线通信模块设计FPGA代码 包括matlab模型文件及verilog源代码-The wireless communication module design including FPGA code matlab verilog model file and source code
FPGA_JOW
- 本设计为学校打铃管理系统，使用VHDL设计，根据打铃功能不同输出不同的音乐,工作模式包括正常上课模式、考试模式、放假模式-The design management system for the school bell, the use of VHDL to design, according to different output different music in Bell functions, working modes including normal class mode, test