资源列表
VHDL-projects
- I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
fpga
- FPGA代码，包含地址译码模块、16位锁存器、AD片选、死区及滤除窄脉冲、过流和短路保护、解除脉冲封锁模块、PWM模块、PWM选择 -FPGA code, including the address decoder module 16 latches, AD chip select, filter out the dead and narrow pulse, overcurrent and short circuit protection, lifting the blockade puls
lvds
- lvds通信协议程序，已调通,并包含一些相关资料-lvds communication protocol procedures have been transferred through, and contains some relevant information
5_ADC_Lab
- 基于altera公司MAX10型FPGA的ADC调试程序-ADC-based debugger altera company MAX 10 type of FPGA
6_USB_to_SDHC_Lab
- 基于altera公司MAX10型FPGA的usb至sdhc通信的调试程序-Altera company based debugger MAX 10 type of FPGA to sdhc usb communication
herisong
- untuk fuzzy logic program
RGB2YUV
- 用verilog语言将RGB颜色空间转换为YUV颜色空间，可以使用的，大家可以试试，初学者可以帮助理解-Convert RGB to YUV with verilog language, can use, you can have a try, can help beginners to understand
RGB2YUV_TB
- 将RGB颜色空间转换为YUV颜色空间的testbench，用verilog写得，可以测试看看。-Convert RGB color space to YUV color space testbench, written in verilog, can test and see.
qwe
- 基于quartus II verilog语言编程，实现有源蜂鸣器播放两只老虎 -Based on quartus ii verilog language programming, the realization of active buzzer playing two tigers
Piplined_RCA
- Pipelined Ripple Carry Adder verilog source file
cla
- Carry Lookahead verilog source file
abs_mode
- abs_mode 2-complement souce and testbench code