资源列表
1
- than dc parameter (saturation current, threshold voltage, etc.) degradation. An electron beam probing was performed on a 64-Mb DRAM chip to detect the influence of gate capacitance variation in dynamic circuit blocks before and after hot-carr
2
- for the first time, the impact of hotcarrier-induced gate capacitance variation on dynamic circuits in a VLSI chip. To investigate the mismatch drift due to the hot-carrier-induced gate capacitance variation, internal probing was performed at
4bit counter
- 4-bit synchronous counter counts sequentially on every clock pulse the resulting outputs count upwards from 0 ( 0000 ) to 15 ( 1111 )
sdram
- FPGA读写SDRAM。里面有详细的注释，供初学者参考，Verilog 语言-FPGA read SDRAM. There are detailed notes, reference for beginners,
DDS
- FPGA实现三通道DDS信号源Verliog程序-FPGA to achieve three-channel DDS signal source Verilog program
uart_rx
- FPGA实现串口接收功能 Verilog语言-Serial reception FPGA Verilog language
uart_tx
- FPGA实现串口发送 Verilog 语言-Serial reception FPGA Verilog language.
basesignal
- 产生一个长为1000的二进制随机序列，“0”的概率为 0.8，”1”的概率为0.2； 对上述数据进行归零AMI编码，脉冲宽度为符号宽度 的50 ，波形采样率为符号率的8倍，画出前20个符 号对应的波形（同时给出前20位信源序列） 改用HDB3码，画出前20个符号对应的波形 改用密勒码，画出前20个符号对应的波形 分别对上述1000个符号的波形进行功率谱估计，画出 功率谱 改变信源“0”的概率，观察AMI码的功率谱变化
cpu
- vhdl实现处理器基本功能，不包括流水线-VHDL to achieve the basic functions of the processor
code
- 某数据传输系统，试图利用300-3400Hz的话音通 道进行载波传输，波形信道为加性高斯白噪声信道。 –采用线性传输，收发两端拟采用滚降系数0.5的根 号升余弦滤波，以解决采样点失真问题。 –以下仿真采用无记忆采样信道模型，其中受器件限 制，复基带采样点平均功率受限为1，复基带采样 点噪声功率为可调参量-A data transmission system, trying to use 300-3400Hz voice channel for carrier transmission, wave
traffic-light
- program fpga, simulation of trafic light. each way have two light, green and red. when one way is green and another way is red. each step have their own time.
divide_by_3
- 时钟的3分频代码，华为中兴面试必备，仿真测试通过-divede by 3