资源列表
sqrt_32bit_non_restoring
- a 32bit non-restoring square root with CSM in VHDL
SHA3-VHDL
- SHA3 VHDL implementation FPGA proven
pipelined_fft_256
- pipelined fft/ifft 256 point ip core
gensin
- 用fpga控制da发一定带宽正弦信号，用vhdl编写，用nco-Fpga controlled by a band-da made a sinusoidal signal, written in vhdl, with nco
fft
- 基于fpga的fft变换，用ip核实现。用vhdl编写-Fpga based fft transform, use ip core implementation. Written in vhdl
cf-fft
- 用ip核实现fft。用vhdl编写。altera的fpga-Ip core implementation using fft. Written in vhdl
PPRAM-test
- 乒乓缓存，用vhdl编写，用fpga内部ram-Ping-pong buffer, using vhdl to write,
jtdverilog
- 交通灯，verilog，VHDL，modelsim-Traffic lights, verilog, VHDL, modelsim ,,,,,,,,,,
project_1
- 显示器显示有信号，能够看到分辨率信息为1280 x 720 @ 60P，显示器显示标准8 色垂直彩条-Display a signal, the resolution information can be seen as 1280 x 720 @ 60P, the display shows the standard 8-color vertical color bar
project_11_first_d1_HDMI
- 本代码将TW2867第一通道输出解复用以后进行BT.656格式的解析，然后将奇偶场合并为一帧存入DDR2，读取的时候使用双线性插值算法，将原始的720 x576的分辨率放大到800x600，然后在HDMI口输出。-This code will TW2867 first channel output demultiplexing after parsing BT.656 format, then the parity occasions and as a frame stored in DDR2,
MATLAB-and-FPGA
- 以Xilinx公司的FPGA为开发平台，采用MATLAB及VHDL语言为开发工具，详细阐述数字通信同步技术的FPGA实现原理、结构、方法以及仿真测试过程-In Xilinx s FPGA development platform, using MATLAB and VHDL language development tools, elaborated synchronous digital communications technology FPGA implementation princip
receive_uart
- fpga串口通信，接收模块程序.verilog语言编写-fpga serial communication, receiving module program