资源列表
URAT-VHDL
- vhdl版本的uart收发程序，方便实用-uart vhdl rx/tx
PSK-mod-demod-VHDL
- vhdl版本的bpsk调制和解调程序，超级实用-bpsk vhdl mod/demod
pseudo-random-number-VHDL
- 伪随机序列发生器的vhdl软件，有m序列和gold序列的算法-pseudo random number generator
113813_CONTADOR_TIEMPO_REAL_1
- vhdl xillin timer source code of an timer based on a Spartan 3E
texample1
- 32-bit shifter, 32-bit.Very goog as a study file.-32-bit shifter, shifter, 32-bit.Very goog as a study file.
i2c_hxj2
- i2c, veitlog, sda, sclk. very good as a study file.
NIOS_Basic
- NIOS相关的基础实验的代码，SYSCLK,TIMESTAMP,LED,SDRAM,INT-NIOS basic experiments related to code, SYSCLK, TIMESTAMP, LED, SDRAM, INT
ADC_pf89
- 本verilog代码通过IIC总线实现了对 PCF8591AD、DA转换芯片的控制。适用于FPGA，亲测可用。-this is used for FPGA to control PCF8591(AD/DA) chip by verilog.
uart
- 用verilog语言编写的串口读写程序，波特率可调，亲测可用。-this is a program for UART by verilog, which is useful.
ALINX9226_DB4CE15_restored
- 本代码是用verilog编写的FPGA控制高速AD9226的程序，亲测可用，供大家参考。-this is a program for FPGA to control AD9226, which is useful by verilog.
FPGA_verilog_uart-
- 基于 FPGA器件设计实现UART的波特率产生器、UART发送器和接收器及其整合电路,，利用Veriolog-HDL语言对这三个功能模块进行描述并加以整合，通过ModelSim仿真，用串口调试程序进行验证，最终实现一个通用异步收发器的设计。-UART baudrate generator, transmitter and receiver and its integrated circuit are implemented by FPGA device. Using Veriolog-HDL d
stepmotor
- 步进电机定位控制系统的VHDL程序与仿真-Stepper motor positioning control system procedures and VHDL simulation