资源列表
FND_TEST
- Hi, This Verilog practice code-Hi, This is Verilog practice code
LCD_TEST
- Hi, This Verilog practice code-Hi, This is Verilog practice code
UART_LED_FND_LCD
- Hi, This Verilog practice code-Hi, This is Verilog practice code
LED_FND_LCD
- Hi, This Verilog practice code-Hi, This is Verilog practice code
UART_TEST
- this is FPGA Verilog project
fnd-clk
- FND, SEGment verilog code
Read_SPI_ADC
- This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 ADC and generates SPI_CLK and SPI_nCS of it and reads 12-bit serial data ADC and returns 12-bit parallel data.-This VHDL code takes a clock, reset, Capture_EN and SPI data LT2315 AD
altera-TimeQuest_User_Guide
- alter时序约束的开发者手册，从官方直接拿到的。-altera timing handbook，directly got xilinx.
xilinx-tcl
- Xilinx脚本约束手册，从官方直接拿到的，对Xilinx FPGA开发很有用的。-Xilinx tcl handbook, directly got Xilinx。
ps2
- ps2键盘扫描程序verilog实现，将按键值转化为扫描值-ps2 keyboard scanner verilog realization, the key will be converted to scan values
LED
- LED等循环点亮，verilog实现功能-LED lights light cycle, verilog to achieve functional
i2c_master_top
- I2C控制总线的顶层描述verilog代码，选项中没有verilog语言，故选择VHDL-The function descr iption of I2C bus top level