资源列表
i2c_master_bit_ctrl
- I2C控制总线主机，按照字节写设计的verilog代码，由于选项中没有verilog这项，因此选择VHDL-I2C control bus master, according to the byte write verilog code design, because the option is not verilog this, so choose VHDL
i2c_master_byte_ctrl
- I2C控制总线按照word写，用verilog实现的主机写功能-I2C control bus according to the word write and write functions implemented by host verilog
i2c_slave_model
- I2C控制总线的重机模型，用于验证I2C设计是否实现了功能描述-I2C bus control heavy machine model, used to verify whether the design implements I2C Functional Descr iption
tst_bench_top
- I2C控制总线的测试平台testbench，用于验证I2C主机冲击交互的正确性-I2C control bus test platform testbench, used to verify the correctness of the interaction I2C master impact
pwm
- 一个宽度脉冲调制pwm的模板，因为是学习使用的，增加了数据输入以便在开发板的led灯中观看实验现象，输入数据越大led的亮度越大-A pulse width modulation pwm template, because it is learning to use, increasing the data input for viewing experimental phenomena in the development board led lamp, the greater the gre
divider7_50
- 一个关于占空比为50 的七分频器，是各个公司面试经常考试的题目-A 50 duty on seven dividers, each company for an interview is often the subject of examination
DDS
- 基于FPGA完成2001年电子设计竞赛直接数字频率合成器，有FPGA部分、MSP430程序以及相互通信的程序，完成题目全部要求-FPGA-based Electronic Design Competition 2001 complete direct digital frequency synthesizer, there is part of the program FPGA, MSP430 procedures and communicate with each other, to comp
multiplier-ROM--FIFO-memory
- 布斯，阵列乘法器，加减交替除法器，以及ROM存储器，FIFO存储器-Booth, array multiplier, divider alternately add and subtract, and ROM memory, FIFO memory
8bit-cpu
- VHDL由简单存储器，计数器等搭建最终实现8位的cpu设计-VHDL realization 8 of cpu design
niyiming
- 矩阵键盘扫描以及数码管自动加一计数显示，适合初学者参考-Matrix keyboard scanning and automatically add a digital counter display, suitable for beginners reference
Fast Vector Multiplication
- Fast Vector Multiplication in VHDL with carry save adders and final ripple carry adder
i2c_master_controller
- Verilig语言描述的I2C Mater控制器的IP核，已经过实践应用，适合于FPGA I2C接口设计应用。本IP核在Altera QII 15.1软件环境下综合，并且包含基于NiosII Gen2处理器的i2c软件驱动代码。-Verilig language I2C Mater described controller IP core, has been the practical application, suitable for FPGA I2C interface design app