资源列表
polynominal-multiplier
- verilog code for polynominal multiplier
4bit-adder
- 4 FIT ADDER FULL EXAMPLE IN VHDL LANGUAGE
wiegand
- Wiegand encoder Recive card number Save card number Mach saved and recived card number Resolve access status
costas
- costas锁相环matlab仿真代码，对costas环的研究和硬件实现具有指导意义。-Costas Phase-Loop MATLAB Code.
VHDL-qiangdaqi
- VHDL语言实现的抢答器功能，源码和原理图都包含在文件内，可以直接在FPGA上运行。-The VHDL Responder function, source code and schematics are included in the file, you can run directly on the FPGA.
spartan3e_test
- Teste Spartan 3e for Spartan 3e board.
contador_off_board
- template of decoder for implemente in vhdl language.
contadorBCD
- 7seg decoder for the best displays
Proj_AND_V1
- Basic vhdl code for and gate logic.
xilinx_DDR3_design_guide
- 关于FPGA的DDR3的设计和应用指导，是个很不错的文档，适应学习FPGA的人进行学习研究-FPGA DDR3 design and application guide
adc7854
- ADS7854 Texas Instruments. The code is built refer to the time sequence datasheet. You should better read the document first-ADS7854 Texas Instruments. The code is built refer to the time sequence datasheet. You should better read the docum
time_check
- 通信主从机双向系统时钟同步，用于扩频、跳频等。由从机发起时间校准请求，主机回复时间信息，达到主从机的时钟同步。-Slave two-way communication between the host system clock synchronization for spread spectrum, frequency hopping and so on. Initiated by the slave time alignment request, the host response time