资源列表
ps2
- 用verilog编写的PS/2通讯协议是一种双向同步串行通讯协议。-Verilog prepared with PS/2 protocol is a bidirectional synchronous serial communication protocol.
ad7266
- 实现FPGA对AD7266的控制，采用Verilog语言编写-FPGA to achieve AD7266 control, using Verilog language
kn_cnt16.v
- 可逆的异步计数器-Reversible asynchronous counter! ! ! ! ! ! ! ! ! ! ! ! !
the_last
- VHDL语言实现两个人掷骰子游戏，最多6次，大者胜则结束游戏并在点阵上显示，一直平手则一直进行直到达到6次。-Achieving the dice game between two people by using VHDL language.The maximum number of times is 6.The game will over when there is a biger one in one time,otherwise,the game will continue until
HDMI_ADV7511
- HDMI芯片ADV7511资料介绍，其中AN1270里面有一套DEMO源码，可以显示。-The information on the chip ADV7511 HDMI, which AN1270 document DEMO inside source confirmed with the DEMO display.
FIFO
- Designed Fifo 16bit Designed Fifo 16bit Designed Fifo 16bit-Designed Fifo 16bit Designed Fifo 16bit Designed Fifo 16bit Designed Fifo 16bit
KinetisIAR
- OSPF协议将网络划分为多个自治域进行管理，路由器根据在自治系统中的角色划分(IAR,ABR,BBR,ASBR)，除IAR外，一个运行OSPF协议的接口状态根据接口的不同类型可划分为 DR: Designated Router BDR: Border Designated Router DROther: Non (DR or BDR)-The OSPF protocol divides the network into several autonomous doma
16x2_lcd_display_driver_latest.tar
- verilog编写的LCD控制器，可以作为LCD的开发-verilog prepared by the LCD controller，It can be used as the development of LCD
my_sd_vga_test
- my_sd_vga_test,SD图像文件存储-my_sd_vga_test, SD image file storage
04_div_clk_1Hz
- verilog HDL 描述分频电路 产生1Hz脉冲方波信号 系统时钟频率50MHz-this is a divide circuit module to get a plus signal of 1Hz
08_counter_white
- verilog HDL 计数器 8位 计数值送数码管显示-this is a verilog file for counter
02_buzzer
- verilog HDL 驱动蜂鸣器 驱动频率可调 驱动频率在1KHz时 无源蜂鸣器声音较大-this is a verilog file to driver the buzzer