资源列表
SegLed
- 数码管的动态显示Ip，你可以例化到设计中需要的工程里-Dynamic digital display Ip, you can instantiate the need to design projects in
subtraction
- 基于FPGA的VERILOG语言的四联十六进制的减法程序-Based on quadruple hexadecimal subtraction process of FPGA VERILOG language
button33
- 基于FPGA的VERILOG语言的3*3按键程序-3* 3 keys based on FPGA VERILOG language program
SECOND
- 基于FPGA的VERILOG的一秒亮一个LED的程序-FPGA-based VERILOG one second light an LED program
VGA
- 本科毕业设计，简易逻辑分析仪，重点在于用CPLD搭建显卡，输出VGA信号驱动显示器显示逻辑波形-A design for LA,use cpld to generate VGA signals.
or_g
- it contains or gate, multiple input output, counter 4-bit 8 bit, parallel adder 4 -bit, 8 bit
nn_last
- Neural Network with FPGA and VHDL codes + Matlab model
Rs232_Vhdl_model
- RS_232 VHDL model for FPGA coded
run_led
- 黑金FPGA开发板配套跑马灯例程，希望和相关朋友分享-Black Gold Marquee FPGA development board supporting routines, and hope to share relevant friends
DDS
- DDS同 DSP（数字信号处理）一样，是一项关键的数字化技术。DDS是直接数字式频率合成器（Direct Digital Synthesizer）的英文缩写。与传统的频率合成器相比，DDS具有低成本、低功耗、高分辨率和快速转换时间等优点，广泛使用在电信与电子仪器领域，是实现设备全数字化的一个关键技术。-DDS with DSP (digital signal processing), is a key digital technology. DDS is a direct digital fre
asyn_fifo
- 本文同步FIFO为TPRAM（两端口RAM，一读一写）。有详细verilog 程序以及说明-FIFO divided by clock domain can be divided into synchronous and asynchronous FIFO FIFO, FIFO read and write only one clock synchronous, asynchronous FIFO read and write were a clock. FIFO divided by
mpi
- MPI接口就是CPU和逻辑之间通信的一个接口，一般使用总线方式，总线一般有两种标准，一种是MOTO模式，另外一种是intel模式。本资料包含verilog程序以及说明-MPI interface is an interface for communication between the CPU and logic, the general way of using the bus, the bus there are two standards, one is the MOTO mode, th