资源列表
10-sequence-detector
- 本系统采用实验箱的48MHz时钟作为输入时钟，将其分频得到计数器计数频率和序列检测器检测序列频率-The system uses a 48MHz clock experimental box as the input clock, to get the counter frequency divider and serial sequence frequency detector
r22sdf_bf1
- Verilog Implementation of Butterfly 1 of R22SDF algorithm
CM
- Verilog Implementation of Complex Mutliplier
CM_WADDR
- Complex multiplier with twiddle factor
WDDRGEN
- Address generation for twiddle factors
WROM
- Twiddle factors in ROM
shuzizhong
- 数字钟，校时较分，显示,用元件例化写的vhdl文件，两个24进制，1个60进制计数器-Digital clock, when the school over the points, show cases with elements of writing vhdl file, two 24-band, a 60-ary counter
lcd12864
- 用FPGA来驱动LCD12864，VHDL语言编写的。-Using FPGA to drive LCD12864，VHDL language
jiaotongdeng
- 理想状态的四路交通灯设计，用CPLD/FPGA驱动的，时间可以更改。-Ideal state of four traffic lights design, CPLD/FPGA-driven, time can be changed.
music
- 用verilog写的《天空之城》的乐曲，内容详细清楚，适合初学者入门-Written by verilog " Laputa" music, detailed clear for beginners
verilog_CPU
- 用verilog写的RISC_CPU，描述文件很详尽，含有测试文件-Written by verilog RISC_CPU, very detailed descr iption of the file containing the test file
vhdl
- 这是一些经典的vhdL源代码，这些代码，用于嵌入式学习，对于想学vhdL的同学很有帮助-This is some classic vhdL source code, the code, for embedded study, is very helpful for students want to learn the vhdL