资源列表
sqrt
- 用verilog实现的开2次方，已经在modelism中经过验证，其时间周期不固定。-Implementation open square with verilog.
Multi_SI
- 用verilog实现的乘法器，可以综合，经过验证。-Implementation multiplication with verilog.
add
- 用verilog实现的可综合的16位和32位加法器，经过验证了。-Implementation addition with verilog.
buffer
- 用verilog实现的buffer，经过了fpga平台验证。-Implement buffer with verilog.
GTX_AURORA_MAIN
- 将数据从板卡网口(Ethernet Mac)经过fifo发至GTX高速串行口 ISE -The data from the network interface card (Ethernet Mac) through fifo GTX sent to high-speed serial port ISE
EMAC_T_GTH
- fpga GTH ISE 数据从板卡网口输入从高速串行收发器（GTH）发出-fpga GTH ISE data input sent from the high-speed serial transceivers (GTH) from the network interface card
GTX_pcie_circle
- ise v6开发板 外部pcei连接线 用GTX收发器实现自环回收发 可以用chipscpoe查看数据-ise v6 development board outside pcei cable with GTX transceivers to achieve self-loop recycling hair can be used to view data chipscpoe
fpga_UART
- 在ISE virtex6 开发板上测试成功的串口收发程序 可用chipscope查看数据 并且包含仿真测试程序-In ISE virtex6 development board test successful serial transceiver can be used to view the data and contains chipscope simulation test program
rgb_to_ycbcr
- rgb 转 ycrcb verilog 语言-rgb to ycrcb
MATLAB
- Matlab code to perform fft
LAB-PROGS1
- VHDL Programmes -1 for dumping on FPGA
updown
- VHDL Programmes -2 for dumping on FPGA