资源列表
behaviour_lot
- lot of program in the behaviour model using vhdl languag that will help for othres
uart16750_latest.tar
- UART Module VHDL CODE TESTED ON FPGA
fsk
- 使用quartus13.0 搭建的FSK调制解调仿真系统使用了DDS技术和正交相关解调。-Quartus13.0 built using FSK modulation and demodulation simulation system uses DDS technology and quadrature coherent demodulation.
pulse_gen
- Pulse generator using VHDL for most of FPGAs
waveform
- The waveform of pulse generator code
control
- The Pipeline SPIN model using VHDL
decode
- The pipeline SPIN VHDL code (decode part)
execute
- The pipeline SPIN VHDL code (execute part)
TimeClock
- 能够在max3上显示24小时，并且具有定时功能，能够设定闹钟，具有正点报时-Max3 can display 24 hours, and has a timer function, be able to set the alarm, with punctual timekeeping
fetch
- The pipeline SPIN VHDL code (fetch part)
memory
- The pipeline SPIN VHDL code (memory part)
clock
- verilog hdl 编写的八位数码管24进制的数字钟，含清零功能-verilog hdl written eight digital tube 24 hex digital clock, with clear function ...