资源列表
Uart
- Uart总线，VHDL语言，硬件描述语言源码-Uart bus, VHDL language, VHDL source code
simpleDivider
- Divider，VHDL语言，硬件描述语言源码-Divider, VHDL language, VHDL source code
simpleRam
- simpleRAM，VHDL语言，硬件描述语言源码-simpleRAM, VHDL language, VHDL source code
transfer
- 基于CPLD的PWM波形的发生器，编程语言为verilog,开发环境为QuartusII.-The CPLD-based PWM waveform generator, the programming language to verilog, development environment for QuartusII.
verilog_all
- Verilog HDL 详细教程，很适合初学者使用。-Verilog HDL detailed tutorial, it is suitable for beginners to use.
in_out_put
- 双向RAM的Verilog程序，能实现双向传数据-The Verilog bidirectional RAM process, to achieve a two-way mass data
ac_control
- air conditioner controller ,with three speeds,cool/heat based on altera fpga
aulto
- 自動販賣機控制電路,具有累計輸入金額和商品控制輸出和自動找零。-Vending machine control circuit, with a total amount of input and control output of goods and give change automatically.
up_down_counter
- 32 bit up/down counter with count enable based on altera fpga
tri_ramp_gen
- an 8-bit triangle/ramp wave generator based on altera fpga
f_divider
- 16-bit frequency divider (32 MHz,16,8,...) based on altera fpga.
freq_syn
- 25-bit frequency synthesizer with 25-bit selection line to generate 96 acurracy signal -25-bit frequency synthesizer with 25-bit selection line to generate 96 acurracy signal