资源列表
HA
- half adder vhdl code
FA_4
- Full adder 4 vhdl code
FA_8
- Full adder 8 vhdl code
FA_16
- Full adder 16 vhdl code
FA_32
- Full adder 32 vhdl code
4_selecteurs
- code source d un decodeur vhdl 3_8-code source d un decodeur vhdl 3_8
FPGA_examples
- 里面共有21个具体实例，附有详细的说明，新手开发的好资料-Which a total of 21 concrete examples, with detailed descr iption of the development of good new information
dianzizhong
- (1) 设置复位功能 (2) 设置启/停功能 (3) 计时精度大于0.01s (4) 最长计时时间为24h （5）闹钟 （6）设定时间 （7）正点报时 -(1) set the reset function (2) set up Kai/stop function (3) is greater than the accuracy time 0.01s (4) the longest time to time 24h (5
VHDlzhilingdaquan
- vhdl 指令和库文件 大全 vhdl 指令和库文件 大全 vhdl 指令和库文件 大全 -vhdl command and library file vhdl Guinness Book instructions and library files and library files vhdl directive vhdl Guinness Book instructions and library files and library files vhdl directive vh
boxin
- 基于DDS的正弦波形发生器频率在DAC芯片速度的的情况下可以实现大范围的连续可调-FPGA
BIN_BCD
- 用硬件描述语音实现二进制数据转换成BCD数据-Using hardware descr iption voice to achieve the binary data into BCD data
freq_count
- 用硬件描述语言实现测量各种信号频率的功能-Using hardware descr iption voice to achieve the functions of measuring frequency