资源列表
FIR_Filter_Base_on_FPGA
- 详尽的讲述了FIR滤波器在FPGA上的实现思路-Detailed story of the FIR filter in FPGA realization of ideas
Altera_timing
- 本文件讲述了Altera的FPGA的时序原理-This document describes Altera' s FPGA timing principle
uart
- 用FPGA实现uart的verilog源码，包含standard framing error, parity control and overrun detection.-The UART design was designed from a standard uart function with a read/write microprocessor interface. It includes standard framing error, parity control and ove
MulAddAbs
- 9 bit multiplier in VHDL
uart
- 使用VERILOG实现自己定以的UART算法，只要自己看懂了，再修给下下就可以使用了-VERILOG use to achieve their own set of UART algorithm, as long as my understood, and then repair to the next can be used under
PS2_IP_CORE
- 该IP核是一个ps2键盘的源代码（vhdl语言）-The IP core is a ps2 keyboard source code (vhdl language)
EDA_tel_counter
- 在EDA教学试验箱上（忘了学校的试验箱型号了）实现电话计费器功能-EDA teaching in the chamber to achieve telephone billing function
cronometro
- This the program of a timer with a accuracy of ms-This is the program of a timer with a accuracy of ms
filtru_fi
- This is a filter fir implemeted in vhdl, i hope it will work :)
uart
- This Verilog file is a desription of an UART, which is a piece of computer hardware that translates data between parallel and serial forms.
cam
- This Verilog desription shows an example for a Content Adressable Memory (CAM)
syn_fifo
- A Verilog descr iption of a synchronous FIFO memory circuit