资源列表
out
- verilog语言编写的米勒解码的输出模块加仿真波形正确了-Miller verilog language decoder output waveform simulation module plus correct
state
- verilog语言编写的miller解码的状态转换模块，这个是仿真成功了的-verilog language miller decoding module state transition, this is the successful simulation of the
miller_decode
- miller整体解码模块没有作成功，但是应该离重点不远。有高手给指点下把-miller overall lack of success of decoding module, but the focus should be not far away. Have a master to the point under the
sy9
- 交通灯 VHDL 程序，程序功能：红灯绿灯各9秒，黄灯3秒-Traffic lights VHDL program, the program features: 9 seconds of red light and green light, 3 seconds of yellow light
LMX2347
- VHDL code for LMX2347(Phase lock loop)
dianyabiao
- 数字电压表vhdl源程序，一个很不错的东西，欢迎大家有点帮助。-Vhdl source digital voltage meter, a very good thing, welcome to some extent.
automat
- automat. in VHDL. This was write in xillinix program
dekoder
- dekoder code s Gray to cod „ 1 from 16”. This is program i VHDL-dekoder code s Gray to cod „ 1 from 16”. This is program i VHDL
Counter_VhdlCode
- it is a simple counter written in vhdl , can be simulated using model sim worked on xillinx for fpga.
Frequency_Divider_VhdlCode
- a very good frequency divider code for fpgas>
A_study_about_FPGA_based_digital_filters
- Digital hilbert transformers for FPGA-based phase-locked loops
avalon_pwm
- altera公司的PWM设计，非常详细！-altera' s PWM design, very detailed!