资源列表
tcm_enc
- 这是一个用VERILOG HDL 编写的TCM信道编码-This is a VERILOG HDL prepared with TCM channel coding
interleaver
- 这是一个用VHDL编写的交织器程序,使用交织器能够使干扰由突发变成随机化-This is a prepared using VHDL interleaver, the use of interleaver enables interference by the sudden randomized into
conv_enc
- 这是一个用VERILOG HDL编写的卷积码程序-This is a VERILOG HDL with the preparation of procedures for the convolutional codes
EDA_usage
- 介绍最基础的概念，和用实例帮助理解，我受益很大-it dwell on concept in relation to vhdl and make sense of it by means of example
top.tar
- 用verilog寫出來的貪食蛇程序,使用開原軟體iverilog進行摹擬-a simple program written in verilog
counter.tar
- 基於verilog 所製成的counter程序，可以向上計數-Verilog made based on the procedures of the counter can count up
ADDER(2)
- simple 16-bet CLA adder
ADDER
- simple 16-bit CSA Adder
lift.vhd
- 用VHDL实现了电梯的模拟程序，实现了自动判断楼层，然后根据客户需求和楼层最近原则，实现自动判断上下行，还有报警，强制开门等功能-Achieved using VHDL elevator simulation program, to determine the realization of an automatic floor, and then based on the principle of demand and the floor recently, automatically dete
eth_phy10
- an ethernet physique sender. it s implemented with spartan 3E starter kit
555
- 四位元乘法器(含TPD) 被乘數:SW(3..0) 乘數: SW(7..4) 積: LEDR(7..0)-Multiplier 4 yuan (including TPD) multiplicand: SW (3 .. 0) multiplier: SW (7 .. 4) plot: LEDR (7 .. 0)
3970988VHDL44
- VHDL实例44个，对于新手来说 勉强可以用-VHDL example 44 for the new force can be used for