资源列表
sys_0820
- 使用VHDL语言描述AD0809芯片功能，实现芯片的硬件描述-The use of VHDL language descr iption AD0809 chip function, the realization of chip hardware descr iption
ramvhdllib_06
- The Free IP Project VHDL Free-RAM Core-The Free IP ProjectVHDL Free-RAM Core
11
- 华为FPGA设计流程指南 华为FPGA设计流程指南-FPGA Design Flow Guide Huawei Huawei FPGA Design Flow Guide
FFT
- FFT的VHDL实现程序 希望对大家有用 -FFT of the VHDL program hope to achieve useful
cpldfpga
- 《CPLDFPGA嵌入式应用开发技术白金手册》源代码-err
VHDL
- 本文介绍了 VHDL语言的学习总结，对于有一定VHDL语言基础的同行们 我想应该能起到一定作用。-This paper introduces the VHDL language summary, for a certain language VHDL-based colleagues I would like to be able to play a role.
UART_VHDL
- 异步串口通信VHDL源代码，通过了验证，最高通信速率可达384-Asynchronous serial communication VHDL source code, through the validation, the maximum communication rate of up to 384
VGA_2c5
- 用VHDL写的，直接在显示器上显示，分辨率为800*600，-Using VHDL written directly in the display shows that a resolution of 800* 600,
mc8051
- 8051 vhdl source code
vhdl_miaobiao
- 用vhdl实现秒表的功能，具有秒表功能,有分、秒显示，后期可以自己添加闹钟的模块。 -Use VHDL to achieve the functions of a stopwatch with a stopwatch function, who, seconds indicates that the latter can add their own alarm clock module.
ethernetblaster-200-202-gpl.tar
- ALtera网络Blaster的映射文件-Altera network mapping document Blaster
baweichufaqi
- 介绍了利用VHDL实现八位除法,采用层次化设计,该除法器采用了VHDL的混合输入方式,将除法器分成若干个子模块后,对各个子模块分别设计,各自生成功能模块完成整体设计,实现了任意八位无符号数的除法。 -Introduced the use of VHDL to achieve eight division, the use of hierarchical design, the divider using VHDL mixed-input methods, will be divided in