资源列表
FPGAuartdebug
- FPGA串口界面调试程序,用VHDL语言实现-FPGA serial debugger interface, using VHDL language implementation
eeprom
- VERILOG实际例程，非常适合初学者学习-VERILOG the actual routine, ideal for beginners to learn
DE2_TV
- 分析了各种视频采集方案的研究现状。对如何采用CCD 摄像头采集高分辨率、高质量的图像以及基于FPGA 的嵌 入式视频图像采集系统的实现方法进行了研究。采用了以摄像头+ 解码芯片模式为采集方案， 针对视频解码芯片 ADV7181B，实现了I2C 总线配置、ITU656 解码、VGA 显示模块的设计。设计的视频采集控制器已经在Altera 公司的CycloneII 系列FPGA(EP2C35)上实现。结果显示本设计具有速度高、成本低、易于集成等优点-Analysis of a variety of
i2s_interface
- - I2S top level test bench. Two transmitters and two receivers are instantiated, one each in slave and master mode. Test result is displayed in the log window, there should be no errors.-- I2S top level test bench. Two transmitters and two receivers
dmx512
- DMX512接收程序C源代码，DMX512接收程序-C source code of the receiving program DMX512, DMX512 receiving program
shuzishizhong
- 此代码是FPGA的数字时钟代码，使用的是verilog语言。-This code is the FPGA' s digital clock code, the use of the verilog language.
Writing_Testbenches_using_System_Verilog
- Testbench creation and development methodology with System Verilog. By Janick Bergeron.
dds-design
- fpga实现dds，实现任意波形输出信，设计代码verilog-dds fpga realization
SDRAM
- sdram的学习使用控制源代码 有需要的同学可以下载-sdram learning to use the control source code can be downloaded to needy students
iic
- 单片机和cpld通信中的用vhdl编写的cpld源程序代码-Cpld single-chip computer and communications cpld prepared using vhdl source code
verilog_18bit_Div
- verilog编写的18位输入高精度的除法器，带说明文件和测试代码。-18 input precision divider verilog prepared with documentation and test code.
i2c
- 标准I2c读写时序，verilog Hdl-Standard I2c read and write timing, verilog Hdl