资源列表
fir
- 比较简单的16位fir滤波器，16阶，Verilog编写-Simple 16-bit fir filter, 16 bands, Verilog prepared
saolei
- 基于FPGA的扫雷游戏，9X9扫雷，我们的游戏包含有五个状态，分别欢迎界面，游戏胜利，简单游戏模式，自定义游戏模式，游戏失败模式。-FPGA-based minesweeper game, 9X9 mine, the game includes five of our state, respectively, the welcome screen, the game is victory, a simple game modes, custom game modes, game failure
rom
- 基于verilog的rom存储器 简单实用 初学者的好材料-Rom memory, based on simple and practical verilog' s good material for beginners
SystemVerilogAssertions
- Srikanth Vijayaraghavan - A Practical Guide for SystemVerilog Assertions-Srikanth Vijayaraghavan- A Practical Guide for SystemVerilog Assertions
sdram_vhd_134
- Xilinx Sdram控制器VHDL源代码-Sound code of Xilinx Sdram Controller based on VHDL
vhdl-vga
- VGA 用FPGA驱动VGA显示器并控制部分及横条、竖棋盘格-VGA monitor with a VGA driver and control the FPGA part and the bar, vertical checkerboard
VHDL对tlc3528控制
- VHDL对tlc3528控制，通过实际的工程验证。
MP3_in_CycloneII
- 在FPGA中实现MP3的解码，verilog的，带说明文档。-In the FPGA to implement MP3 decoding, verilog, and with documentation.
ram_Test
- RAM读写控制器，用verilog实现的简单易懂的RAMROMsram控制核-Controller RAM read and write, using verilog implementation of easy-to-understand control of nuclear RAMROMsram
color_conv
- BT656,YCBCR数据格式转换成VGA(888)数据算法，-BT656, YCBCR data format converted into VGA (888) data algorithm,
VHDL
- 8位相等比较器含源代码，用VHDL语言编写，具体很高的实用性，供读者参考-8, phase comparator, such as with the source code, using VHDL language, the specific relevance of a high for the reader is referred to
cpu
- verilog编写的简单的CPU，用于参考，已经过仿真-verilog prepared by a simple CPU, for reference, has been simulation