资源列表
IPcore
- 基于EP3C25的Altera SDI IP核的使用-EP3C25 Altera SDI IP
8051IP_Verilog
- 8051核，verilog实现。可以直接用在FPGA中，在此基础上可以和用真正的8051一样的进行单片机的学习。-8051 Nuclear, verilog achieve. Can be directly used in the FPGA, in this basis can be used as the real conduct of the 8051 single-chip learning.
eth_send
- 清华大学sdr项目，网口代码。Verilog编写。很实用。希望大家喜欢。-Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.
VERILOG-USB2.0IP-core
- 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-VERILOG language with a complete development of USB2.0 IP core source code, including files, simulation files
2
- 详细功能、包含内容说明 :时钟2倍频vhdl描述,-It very important data
led8x8
- 8x8点阵滚动字幕显示驱动 verilog-8x8 dot matrix display driver verilog marquee
codeb_generator5.6
- B码校时（B码的产生）用来产生B码，实现B码校时 使设备进行同步。
xilinx_fpga
- 赛林思fpga开发实例包括verilog语言和vhdl语言-The Sailin Si fpga development Examples include the verilog language and vhdl language
lab1_VHDL
- VHDL数字系统设计工程实践，包含实验的原理，真值表和结构图描述，以及相关的VHDL代码。-VHDL digital system design engineering practice, including the principle of the experiment, truth table and chart descr iptions, and associated VHDL code.
kt3tuo
- 基于FPGA的多功能数字钟系统（层次化设计）拓展功能包括：报时、校时校分、6到18点时段控制亮灯-Multi-functional digital clock system (hierarchical design) in the FPGA-based development features include: timekeeping, school Calibration of 6-18 hours to control lighting
alu_74181
- 4 bit alu to replace a 74LS181
p2s
- 并串转换模块，内含有另个.vhd文件。一个是自己写的比较简单 另一个是参考的。-And the string conversion module, which contains another one. Vhd file. One is its relatively simple to write the other is the reference.