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numberword
- 计数器控制程序，希望能够给大家帮助！文件在ＭＡＸ ＰＬＵＳ下开发，调试通过-counter control procedures, we hope to be able to help! MAX PLUS document under development, through debugging
ref-ualaw
- A率/u率 压缩与解压缩的IP核，。 # 由AHDL语言写成，可在MaxplusII和QuartusII中使用，源代码加密。-A rate / u rate compression and decompression of the IP core,. By AHDL # languages, and the Quartus II MaxplusII use, the source code encryption.
statem
- 元件例化与层次设计，verilog 实例说明-components cases with the level of design, Verilog example
200512251221612004
- 本文件是altera公司fpga的ip核，从国外网站下载的免费源码。-ALTERA This document is the company they simply ip nuclear, downloaded from the web free source.
counter16
- 风格非常好 一六位计数器 无密码 质量很高-style very good counter-16 high quality Password
可综合的vhdl设计特点
- 可综合的vhdl设计特点.pdf-synthesizable VHDL design features. Pdf
1024点FFT快速傅立叶变换(vhdl)
- 1024点FFT快速傅立叶变换,(vhdl代码)-1024-point FFT vhdl
8255
- 8255参考设计VHDL源代码-The sound code of 8255 reference design based on VHDL
State.Machine
- State.Machine.Coding.Styles.for.Synthesis（状态机，英文,VHDL）-State.Machine.Coding.Styles.for.Synthesis (FSM, English, VHDL)
VHDL的基本数学运算库
- VHDL的基本数学运算库,非常好用-VHDL basic arithmetic library, a very handy! !
register reallocation
- 关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
Silicon_Integrity，VHDL
- 信号完整性，设计FPGA的基础-signal integrity, design based FPGA