资源列表
102416FFTVHDL
- 1024点，16位FFT VHDL 程序。1024点，16位FFT VHDL 程序-1024, 16 FFT VHDL procedures. 1024, 16 FFT VHDL procedures
dds_quicklogic
- 高手写的VHDL源码，实现DDS跳频器功能 请大家多提意见-experts write VHDL source code, the frequency-hopping DDS functionality Please speak up
szgysj
- 工业设计-industrial design
serial_VHDL
- FPGA进行串口通信的程序 VHDL编写的 -FPGA for serial communication procedure prepared by the VHDL
videodigitalsignalscontroller
- 用fpga技术实现基本的视频信号处理：主题程序；视频图象数据采集程序；sram的读写控制；测试程序-they simply use the basic technology of video signal processing : theme; Video data acquisition procedures; SRAM literacy control; test procedures
counter&adder
- counter and adder program by vhdl. Just enjoy it!-counter and adder program by VHDL. Just enj oy it!
vhdl_fifo
- 用vhdl编写的fifo队列.可以在maxplus2平台上使用.-using VHDL fifo prepared by the cohort. Maxplus2 platform can be used.
UP3_CLOCK
- 一个很小的时钟代码 一个很小的时钟代码-a small clock code, a small clock code, a small clock code a small clock code
EDA_clock1
- 电子秒表电路，可在开发版上下载运行，verlog开发-electronic stopwatch circuit may download the development version running verlog Development
vhdl-2
- UART 的VHDL源代码。可在ISE, Max-Plus II,等开发环境下实现。-UART VHDL source code. The ISE, Max-Plus II, and other development environments under.
gold
- SRL16是Virtex器件中的一个移位寄存器查找表。它有4个输入用来选择输出序列的长度。使用XCV50-6器件实现，共占用5个Slice。用来生成gold码。-SRL16 Virtex devices is a shift register lookup table. It has four input used to select the output sequence length. Use XCV50-6 device, occupying a total of five Slice.
VHDL-Clock
- 用VHDL语言写的时钟程序。采用模块化编程。可在EPM7128芯片上下载。编译环境可用Maxplus或Quartus。-write VHDL clock procedures. Modular programming. The EPM7128 chips download. Build environment or Quartus Maxplus available.