资源列表
blaster-wh
- 自己做的Altera下载线，老早了，protel98制板。-wh-own download Altera's line, long ago, protel98 Cricket. - Wh
Evita_Verilog
- Verilog 的非常好用易懂的教学软件。-Verilog very handy and easy to teaching software.
Evita_VHDL
- VHDL 的非常好用易懂的教学软件。大家试试看。-VHDL very handy and easy to teaching software. We try.
CPLD_DMA
- 这是一款USB接口ISP1582器件实现DMA传输的辅助电路的硬件设计源代码-This is a ISP1582 USB device DMA transmission of the auxiliary circuit hardware design source code
RAMINCREASE
- 这是利用ＣＰＬＤ做ＤＳＰ的存储器扩展的源文件。-CPLD This is done using the DSP memory expansion of the source document.
primetime
- 这是ＶＨＤＬ语言编写的延时测试程序，用来测定ＣＰＬＤ的性能指标-This is the VHDL language delay the test procedure used to determine the performance CPLD
mt48lc2m32b2
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
SDRAM_C
- SDRAM控制核，已经经过测试，完全可以稍加修改后应用-SDRAM control nuclear, has been tested, we can use a slightly modified
time_clock
- 实用闹钟的verilog代码。不是vhdl的！经过ldv验证-practical alarm the Verilog code. VHDL is not! After certification ldv
Verilog-statemachine
- 利用Verilog编程实现状态机的例子。很不错的。-use Verilog Programming state machine example. Very good.
EDK_timer_ex
- EDK_timer_ex定时器计数器的开发 -EDK_timer_ex timer counter Development
wodevhdl
- vhdl练习实例。在maxplus2中编写，编译通过，正确。-VHDL practice examples. In maxplus2 prepare, compile and correct.