资源列表
clock_matrix_rg
- the hien tinh cam cua nhan loai
工作簿1
- 主要关于合肥工业大学计算机方面的知识，有数据结构，计算机组成原理，java，面向对象，(Just hole teacher talk, so that six new development of the party, you find a time, with the volunteer book, together to find the blue Secretary talk, @ Wang Kuo, you're responsible for this thing, a common
crossbar
- 2 master - 2 slave communication crossbar
nokia ring tone RTLL
- Nokia ringtones 8051
yii-account-module-master (1)
- mkjhkjh kjhjkhjkhk kjhkjh kjhkj
ef48dc75a9a60030c622898a19b0f2d6 (1)
- 内有关于循环码的编码器的程序语言，可用quartus ii打开(There is a program language on the encoder of the loop code, which can be opened with Quartus II)
kdtree-scala-master
- Kd tree implementation in scala spark language
fifo
- 基于verilog HDL的fifo设计与测试，包含设计与测试代码，以及简单的makefile编写。整个平台是基于linux操作，仿真平台是基于SYNOPSYS的vcs工具。(Based on verilog HDL fifo design and testing, including the design and test code, and simple makefile.The platform is based on Linux operating, the simulation pla
数字钟
- 数字钟(Digital clock)
SPI
- 用Verilog语言实现FPGA串口通信(Using Verilog language to realize FPGA serial communication)
aes_128pprm3
- 基于PPRM3S盒的128位AES密码算法Verilog代码(Verilog code for 128 bit AES cipher based on PPRM3S box)
FPGA实现AD8556采集程序设计
- 基于ADS8556的FPGA数据采集程序设计。(The design of FPGA data acquisition program based on ADS8556.)