资源列表
myprjct
- 一个锁存器，单纯简单的，没什么好用的，以后再穿好的上来-A latch, simple simple, nothing easy to use, wear good up after
InitialcalculationsUsingCVI
- 本程序使用CVI计算51单片机定时/计数器初值，输入晶振和定时时间，可自动算出初值-This procedure calculated using CVI Singlechip 51 timer/counter initial value, type and timing crystal time, can automatically calculate the initial value
Bucys3
- adaptive controling is a very good way to control of complex systems
Designing_Multi-Asynchronous_Clock_Designs
- 这里介绍了如何使用多时钟树的方法，这在FPGA中经常用到-This paper describes how to use multi-way clock tree, which is often used in FPGA
VB6.0
- 基于VB6.0的任意波形发生器 下载波形数据时，闭合右边开关，波形数据传输完毕时打开即可。 左边开关为选择波形通道，有31个状态，须复位电路有效。 本仿真须安装虚拟串口。-VB6.0-based arbitrary waveform generator download waveform data, closed the right switch, open when the waveform data can be completed. The left switch
68013A_BULK_TRANS
- CY68013A异步BULK传输范例，严格按照时序描述来进行读写，对fifo实现读写，功能完善。-CY68013A asynchronous BULK transmission model, in strict accordance with the temporal descr iption to read and write, read and write to the FIFO implementation, perfect function.
xs3togray
- vhdl code for excess3 to gray code
d_ECT
- 飞思卡尔单片机 XS128 ECT模块 的具体实现 已调试,直接可用-Freescale MCU XS128 ECT concrete realization of the module have been debugging directly available
irda1204
- pic33fj256gp710 uart
RTCC.zip
- PIc24 Real time clock with alarm and 10sec interruptions,PIc24 Real time clock with alarm and 10sec interruptions
Verilog-HDL-Coding
- Motorala推荐的Verilog代码规范。对于VerilogHDL语言编写很有借鉴意义。-Motorala recommended Verilog code specifications. VerilogHDL language is useful for reference.
IPC-7251-Padstack-Charts
- PCB板通孔焊盘制作标准-IPC-7251,标准资料-The PCB through-hole pad production standard-IPC-7251, standard data