资源列表
synthesizable_Verilog_syntax_and_semantics
- 《可综合的Verilog语法》国外著名大学老师编写，对于理解verilog HDL文件的可综合与不可综合会有帮助。-synthesizable Verilog syntax and semantics,by teachers from university of Cambridge,It is userful for verilog HDL design.
FreeRTOS_HC(S)08_Version_1.0
- 这是CodeWarrior环境下基于freescale单片机上的实时操作系统代码.-This is the CodeWarrior environment freescale microcontroller based on the real-time operation system code.
Windows_Embedded_CE_6
- Windows_Embedded CE_ 6.0,说名字的话，大家就可以猜到了，最新的WINCE6.0-Windows_Embedded CE_ 6.0, said the name, we can be guessed, the latest WINCE6.0
Can_be_integrated_Verilog_syntax
- 可综合的Verilog语法（剑桥大学，影印）, 语法全面，适合学习或研发人员参考-Can be integrated Verilog syntax (Cambridge, photocopying), grammar comprehensive reference for learning or R & D personnel
verilog
- 可综合的Verilog语法（剑桥大学，影印）-Can be integrated Verilog syntax (Cambridge, photocopying)
graphics-lcd-library.tar
- Graphics display library. 132x132 st7637 controller based and 240x320 SPFD5408B or ILI9325 like controller based.
I2C
- I2C总线的实例程序，用PROTEUS+KEIL演示-Examples of I2C bus procedures, PROTEUS+ KEIL presentation with
sed1565
- 控制器资料sed1565,LCD12864说明书-Controller data sed1565, LCD12864 manual
Synthesizable-Verilog-syntax
- 可综合的Verilog语法（剑桥大学，影印）.-Synthesizable Verilog syntax (Cambridge, photocopying).
dianzizhong
- 单片机电子钟，用C语言开发。 设计制作一个电子钟并且能够显示日历，用LED数码管直接显示，能够通过按键调整时间、年月日，功能为按第一个键为Mode（模式）键，被调整的相应调整区域开始闪烁，第二个键（Add键）加一，第三个（Sub键）减一，中间的键（Add键）可以使时分秒和年月日相互切换。-MCU clock, using C language development. Designed an electronic clock and can display a calendar, with
de0_Schematic
- Altera FPGA DE0的原理图,包含一些经典的FPGA设计电路及相关的接口-Altera FPGA DE0 schematic, contains some classic FPGA design the interface circuit and related
DSP2812
- DSP2812 学习版电路原理，最小系统版-DSP2812 learning version of the circuit principle, the smallest system version