资源列表
04_div_clk_1Hz
- verilog HDL 描述分频电路 产生1Hz脉冲方波信号 系统时钟频率50MHz-this is a divide circuit module to get a plus signal of 1Hz
Examples-of--SEED-dsp-5416-Program
- 震撼贡献，学习DSP非常实用的源代码，全部均是能完整运行，是学校从公司花钱买的，基于CCS2.2版本。-Shock contribution, a very useful learning DSP source code, all of which are able to complete running the school money to buy from the company, based CCS2.2 version.
VerilogHDL_alarmclock
- 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置，源代码对FPGA和CPLD学习者价值很高，
UpgradeTool
- qrtqetvg5qybw5ybsercv
EELiodLinux
- 日到电子上机指导书，含有众多指导实验，包括led gprs等
FPGA_DSPbuilder
- DSPbuilder可直接在MATLAB中调用，生成可执行的VHDL语言。-DSPbuilder can be directly invoked in MATLAB to generate executable VHDL language.
2
- 嵌入式数字硬盘录像机的软件应用，对大家有帮助！-Embedded Digital Video Recorder software applications, to help everyone!
XINHAOFASHENGQI
- 本信号发生器，采用Atmel公司单片机开发板，在AVRSTUDIO编译环境中，可通过按键控制产生三角波、据赤波、方波和改变频率，并显示在LCD上。-The signal generator, using Atmel' s microcontroller development board, in AVRSTUDIO compilation environment, you can control the triangular wave generated by the keys, acco
ESPlorer
- It is source code for esplorer for arduino platform.
ke
- 单片机C语言程序,供大家一起学习，程序代码-straight,loop,flag!
01_run_led
- FPGA源码资料 采用的是EP4CE15F17C8N这个硬件平台 流水灯的源码-FPGA source code is the use of EP4CE15F17C8N hardware platform for water lamp source
keil_jiaochen
- 自己收集的多本Keil开发环境的的教程，于初学者或者提高都有一定帮助。-Have collected more than the Keil development environment of the tutorial, for beginners or have some help to improve.