资源列表
LUdecompose
- 基于verilog的LU分解,本文件包括详细的程序代码，运行文件，以及详细的文档-LU decompose based on verilog
pinlvji
- 用4位十进制计数器对用户输入时钟信号进行计数，计数间隔为1秒钟。计数满1秒钟后将计数值（即频率值）所存到4位寄存器中显示，并将计数器清0，在进行下一次计数。 频率计由三种模块组成：testctl为控制模块，由1Hz其准产生rst_cnt,load,cnt_en信号；cnt10为带清0及计数允许的十进制计数器；reg4b为四位寄存器。 -With four decimal counter input clock signal to the user to count, count one
STM32F407——TIM3正交编码器
- 单片机应用中，比较实用的C语言实例，编码器正交编码(SCM application, a more practical example of C language)
LCDCode
- 用51单片机控制的17寸液晶显示器源程序-51 MCU control with 17-inch LCD monitor source code
LDPC-Verilog
- LDPC的verilog程序，含有编解码的过程-LDPC verilog
Real-Time-Concepts-for-Embedded-Systems
- 为风河工程师亲自根据VxWorks实时操作系统的特点而编写的实时系统方面的书籍，非常专业-Engineer for Wind River VxWorks real-time operating system based on personal characteristics of the real-time systems and the preparation of books, very professional
AN_KIT_RS232
- 采用C语言在Microblaze下开发的FPGA程序，适用于Xilinx Spartan3AN 开发板-Using C language in Microblaze FPGA development program for Xilinx Spartan3AN development board
TI-DSPexamples-program
- 含有TI dsp系统的各个主要芯片系列器件的例子程序-Examples of each of the major chip family of devices with TI DSP system procedures
STC
- STC系列单片机资料，包括11，12C系列-STC Series MCU information, including the 11,12 C Series
MAX197-5STATE
- 使用Verilog在Quartus II下编写的MAX197 AD采集程序，系统时钟50MHz。经测试完全可使用。-Use Verilog in Quartus II prepared MAX197 AD collection procedures, the system clock 50MHz. Tested fully use.
MTK6228_hardware
- 6228硬件主要资料，包括完整的原理图，PCB图和datasheet-6228 hardware key information, including a complete schematic, PCB maps and datasheet
CC1101-LAYOUT
- 这是参考官方设计手册做的一个CC1101模块，实测有效直线通信距离200米，绘制环境AD16(附51，MSP430程序设计参考资料以及TI PCB参考设计)-This is the official reference manual designed to do a CC1101 module, found effective communication distance of 200 meters straight draw Environment AD16 (Annex 51, MSP430