资源列表
RGB2YCbCr
- 视频格式空间转换 verilog语言实现-Space conversion video format verilog language
h_adder
- 采用VHDL语言编写的半加器程序，希望对大家有用。-VHDL language using the half adder program, we hope to be useful.
DSP_INTERFACE
- DSP与FPGA时序接口模块，已经经过测试，保证读写稳定-The Interface of DSP to FPGA
cd53_up
- dwt with vhdl for jpeg2000
fpgaconvert
- 将xilinx 的fpga配置bit文件转换为c语言文件，通过cpu配置fpga-translate？i can t
IIR-digital-filter-design-FPGA
- 基于FPGA的IIR低通数字滤波器设计 IIR low-pass digital filter design based on FPGA-IIR low-pass digital filter design based on FPGA
RGB-to-yuv422
- verilog语言写的视频数据处理相关的代码。实现功能为将RGB数据转化为BT656数据。-verilog language to write video data processing related to the code. Functions for the RGB data into the BT656 data.
v-watch
- 基于fpga的数字电压表的设计，包括ad转换，bcd码转换，分频，3选1模块，小数点生成模块，显示模块组成。-Based on the FPGA digital voltage meter design, including AD conversion, BCD code conversion, frequency,3 choose1module, a decimal point generating module, display module.
an-8-bit-left-shift-register
- 使用VHDL语言设计一个8 位左移移位寄存器。并给出了仿真波形。-Using VHDL to design an 8-bit left shift register. And simulation waveforms.
dac
- 基于fpga的数模转换器接口设计，转换数码管上显示的数字电压-Convert the digital voltage is displayed on the digital tube based the fpga DAC interface design,
oob_control
- sata协议物理层的OOB带外信号控制实现的VHDL代码-the sata protocol physical layer OOB band signal control VHDL code
anolog_conversion.rar
- analog to digital data conversion using vhdl,analog to digital data conversion using vhdl