资源列表
hua
- 使用verilog编写的AD7810控制器，经过了仿真验证(The AD7810 controller written by Verilog has been verified by simulation)
jtag fsm
- jtag接口的状态机实现，李庆华《通信IC设计》随机代码(State machine implementation of JTAG interface)
FIFO_ASY
- 异步FIFO，利用格雷码作异步FIFO指针减少亚稳态产生，利用同步寄存器放置亚稳态的级联传播。(Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.)
encoder
- 基于1553B 模块 decoder 程序(decode_1553b_model.v)
FIFO
- 用verilog语言的实现FIFO存储器，以先进先出的方式处理数据(The FIFO memory is implemented in Verilog language, and data is processed in FIFO)
shujuchuli
- FPGA处理AD转换数据，程序简单实用,带注释标注(FPGA processing AD conversion data, the program is simple and practical)
seq
- 实现序列检测功能，新手编程，已经在modelsim里检验过了功能完整，内附模块化testbench(Sequence detection function, novice programming)
day1
- 《四则运算小计算器设计过程实录》day1(verilog HDL code for day1,7 .rar documents in total.For more code u can put ur eye on my account.)
full_license
- quartus9.0 全功能license(quartus9.0 full license)
c_crc16
- CRC 16 development code
Digital_Clock
- 用verilog写的数字时钟代码，亲测可用，可自行编写test bench进行仿真(Written in Verilog digital clock code, pro test available, you can write your own test bench for simulation)
fenpin
- 实现奇数、偶数分频,fpga,Verilog,时钟分频(clock divider,frequency division)