资源列表
adder_4bits
- 实现四位先行加法器的功能以及测试代码，其中adder_4bits.v为模块代码，adder_4bits—_tb.v为测试代码。还附加 部分其他加法器测试代码(Implement the function of four bit first adder and test code)
highperformance
- 最大公约数（GCD）stein算法实现，高性能流水线实现(The greatest common divisor (GCD) stein algorithm, high performance pipeline implementation.)
8b10_dec.tar
- 10-bit to 8-bit decoder
8b10_enc.tar
- 8-bit to 10-bit encoder
ADC_TLC549
- fpga TLC549ADC驱动程序,驱动ADC模块采集电压信息(FPGA Verilog Code for TLC549 Caluc ADC Value)
sim
- 调试bcm5396，写入和读取内部寄存器功能。功能验证可以用(Debug bcm5396, write and read the internal register function. Functional validation can be used)
lab1
- 在vivado上测试通过的fpga流水灯(Test the passing FPGA flow lamp on vivado)
hamming_fsk
- 基于汉明编码的fsk传输系统，含编码，调制，解调，解码等模块。(FSK transmission system based on Hamming code, including encoding, modulation, demodulation, decoding and other modules.)
serial
- FPGA实现232通讯，用verilog语言(RS232 communication design in FPGA with verilog)
ACCx42_AvalonST_Input
- This module does pipelined accumulate operation with 42 bit int value, usually used in dsp, Proved in Altera Stratix FPGA devices
APBL
- APBL通信协议的FPGA设计，适用于高速通讯(APBL communication protocol FPGA verilog design)
AHB_LITE
- AHB_Lite 通信协议的FPGA Verilog 设计(AHB_Lite communication protocol Verilog design in FPGA)